author={Ammendola}, R. and {Biagioni}, A. and {Frezza}, O. and {Lo Cicero}, F. and {Lonardo}, A. and {Stanislao Paolucci}, P. and {Rossetti}, D. and {Salamon}, A. and {Salina}, G. and {Simula}, F. and {Tosoratto}, L. and {Vicini}, P.},
title={“{APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters}”},
We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design allows us to build a low latency, high bandwidth PC cluster, the APEnet+ network, the new generation of our cost-effective, tens-of-thousands-scalable cluster network architecture. Some test results and characterization of data transmission of a complete testbench, based on a commercial development card mounting an Altera FPGA, are provided.