Mersenne Twister Random Number Generation on FPGA, CPU and GPU
The University of Edinburgh, School of Engineering, Edinburgh, UK
2009 NASAESA Conference on Adaptive Hardware and Systems (2009) Publisher: Ieee, Pages: 460-464
@conference{tian2009mersenne,
title={Mersenne twister random number generation on FPGA, CPU and GPU},
author={Tian, X. and Benkrid, K.},
booktitle={2009 NASA/ESA Conference on Adaptive Hardware and Systems},
pages={460–464},
year={2009},
organization={IEEE}
}
Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intel Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25x and ~9x respectively. Moreover, when using the same amount of energy, the FPGA can generate 37x and 35x more Mersenne Twister random samples than the CPU and the GPU, respectively.
March 20, 2011 by hgpu
