high performance computing on graphics processing units: hgpu.org

Parallel processor architectures are a promising solution to provide the required computing performance for current and future high performance applications. Certainly, the impact on the computational power of such a parallel computer system is related to the inherent parallelism of the algorithm to be implemented. The implementation of an algorithm onto a parallel computer architecture, requires from the developers a good knowledge of the underlying hardware in order to exploit the effect of the parallelization most beneficial. In order to hide as good as possible the complexity of the hardware from the developers, novel programming languages for parallel computers were developed. For example the programming models CUDA, OpenMP, OpenCL, Open GL and MPI are targeting novel multiprocessor system-on-chip architectures like the Intel Single Chip Cloud Computer with 48 cores or the Nvidia Tesla processors with hundreds of processor cores. If a new hardware architecture is invented and developed, it is always beneficial to follow standards in programming models in order to keep a compatibility to already developed programs. A novel runtime adaptive multiprocessor system-on-chip is the RAMPSoC. RAMPSoC combines the benefits of multiprocessors and reconfigurable hardware in one system and is therefore of high importance for future system design. In order to align the RAMPSoC approach to current standards, a support for Message Passing Interface (MPI) was included recently. This important step allows now to re-use already existing source code written with MPI extensions on a runtime adaptive platform.