FSimGP^2: An Efficient Fault Simulator with GPGPU

Min Li, M.S. Hsiao
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
19th IEEE Asian Test Symposium (ATS), 2010


   title={FSimGP^{} 2: An Efficient Fault Simulator with GPGPU},

   author={Li, M. and Hsiao, M.S.},

   booktitle={2010 19th IEEE Asian Test Symposium},






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General Purpose computing on Graphical Processing Units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. But GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA Compute Unified Device Architecture (CUDA). A novel three-dimensional parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. The experimental results demonstrate a speedup of up to 42x compared to another GPU-based fault simulator and up to 53x over a state-of-the-art algorithm on conventional processor architectures.
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