A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor
KAIST, Daejeon, South Korea
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011
@conference{oh201157mw,
title={A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor},
author={Oh, J. and Park, J. and Kim, G. and Lee, S. and Yoo, H.J.},
booktitle={Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International},
pages={130–132},
issn={0193-6530},
organization={IEEE}
}
Artificial intelligence (Al) functions are becoming important in smartphones, portable game consoles, and robots for such intelligent applications as object detection, recognition, and human-computer interfaces (HCI). Most of these functions are realized in software with neural networks (NN) and fuzzy systems (FS), but due to power and speed limitations, a hardware solution is needed. For example, software implementations of object-recognition algorithms like SIFT consume ~10W and ~1s delay even on a 2.4GHz PC CPU. Previously, GPGPUs or ASICs were used to realize Al functions. But GPGPUs just emulate NN/FS with many processing elements to speed up the software, while still consuming a large amount of power. On the other hand, low-power ASICs have been mostly dedicated stand-alone processors, not suitable to be ported into many different systems. This paper presents a portable embedded neuro-fuzzy accelerator: the intelligent reconfigurable integrated system (IRIS), which realizes low power consumption and high-speed recognition, prediction and optimization for Al applications.
May 4, 2011 by hgpu
