Case Study: GPU-based implementation of sequence pair based floorplanning using CUDA
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
@inproceedings{choi2010case,
title={Case Study: GPU-based implementation of sequence pair based floorplanning using CUDA},
author={Choi, W.H. and Liu, X.},
booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
pages={917–920},
year={2010},
organization={IEEE}
}
In this paper, we demonstrate that runtime of VLSI Computer-aided design (CAD) applications can be successfully reduced with parallel programming in conjunction with Graphic Processing Units (GPUs). Particularly, we apply GPU-based computing to the sequence pair based floorplanning algorithm. In addition to reducing runtime, we focus on the minimization of changes in code structure in order to reduce programming efforts. With less than 16 percent of the original program modified, the runtime of the floorplanning algorithm shows an average speedup of 13.5 without performance degradation.
May 15, 2011 by hgpu
