Extremely fast simulator for decoding LDPC codes

S.F. Yau, T.L. Wong, F.C.M. Lau
Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Hong Kong, China
13th International Conference on Advanced Communication Technology (ICACT), 2011


   title={Extremely fast simulator for decoding LDPC codes},

   author={Yau, SF and Wong, TL and Lau, FCM},

   booktitle={Advanced Communication Technology (ICACT), 2011 13th International Conference on},





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Decoding low-density parity-check (LDPC) codes requires a lot of computation time, particularly when bit error rates as low as 10-9 are needed. In this paper, we improve the simulation speed by making use of an inexpensive graphics processing unit (GPU). A dedicated program is written to utilize the hardware resources in the GPU to decode LDPC codes in a parallel manner. Codes with rate 1/2 and length 2, 304 and 10, 008 are simulated by both GPU and central processing unit (CPU). We also show the average iteration time when LDPC codes with length 15, 000 and 20, 000 are simulated.
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