Unifying stream based and reconfigurable computing to design application accelerators

Bruno Francisco, Frederico Pratas, Leonel Sousa
INESC-ID, IST TULisbon, Rua Alves Redol, 9, 1000-029 Lisboa, Portugal
18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010


   title={Unifying stream based and reconfigurable computing to design application accelerators},

   author={Francisco, B. and Pratas, F. and Sousa, L.},

   booktitle={VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP},





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To facilitate the design of hardware accelerators we have proposed the adoption of the stream-based computing model and the usage of Graphics Processing Units (GPUs) as prototyping platforms. This model exposes the maximum data parallelism available in the applications and decouples computation from memory accesses. In this paper we go a step further in showing how to use the proposed methodology to accelerate a widely used MrBayes bioinformatics application. In particular, we provide design and implementation procedures and details. We analyze problems faced during the implementation such as the connectivity between the CPU and the FPGA and we provide possible solutions. Experimental results show that our mapping of the stream-based program for the GPU into hardware structures leads to real improvements in performance, scalability and cost. The hardware accelerator allows to reduce the respective processing time up to more that two hundred times while the whole bioinformatics application can run 1.44 faster than by using only the host.
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