Pricing the American Option Using Reconfigurable Hardware
Electrical Engineering Department, RPI, 110 8th Street, Troy, NY 12180, USA
International Conference on Computational Science and Engineering, 2009. CSE ’09
@inproceedings{wynnyk2009pricing,
title={Pricing the American Option Using Reconfigurable Hardware},
author={Wynnyk, C. and Magdon-Ismail, M.},
booktitle={2009 International Conference on Computational Science and Engineering},
pages={532–536},
year={2009},
organization={IEEE}
}
We present a novel reconfigurable hardware architecture for accelerating American option pricing using the binomial lattice algorithm. The architecture provides double precision floating point pricing, evaluating up to N = 64,000 time steps in the binomial lattice. Advanced memory management techniques and optimized control logic allow for 4-way parallelism on a single-asset evaluation. These techniques achieve a 73-times speedup over an optimized CPU implementation, and a considerable improvement over the best previous reconfigurable hardware implementation. A significant advantage of our approach is that the speed up is on a per asset basis whereas all previous approaches on FPGA and GPU architectures achieve their speed up by evaluating many assets in parallel.
August 10, 2011 by hgpu
