Towards metaprogramming for parallel systems on a chip
Department of Computing, Imperial College London, 180 Queen’s Gate, London, SW7 2AZ, UK
EURO-PAR 2009 – Parallel Processing Workshops, Lecture Notes in Computer Science, 2010, Volume 6043/2010, 36-45
@inproceedings{howes2010towards,
title={Towards metaprogramming for parallel systems on a chip},
author={Howes, L. and Lokhmotov, A. and Donaldson, A. and Kelly, P.},
booktitle={Euro-Par 2009–Parallel Processing Workshops},
pages={36–45},
year={2010},
organization={Springer}
}
We demonstrate that the performance of commodity parallel systems significantly depends on low-level details, such as storage layout and iteration space mapping, which motivates the need for tools and techniques that separate a high-level algorithm description from low-level mapping and tuning. We propose to build a tool based on the concept of decoupled Access/Execute metadata which allow the programmer to specify both execution constraints and memory access pattern of a computation kernel.
August 22, 2011 by hgpu
