5289

Hera-JVM: a runtime system for heterogeneous multi-core architectures

Ross McIlroy, Joe Sventek
Microsoft Research, Cambridge, United Kingdom
Proceedings of the ACM international conference on Object oriented programming systems languages and applications, OOPSLA ’10, 2010

@inproceedings{mcilroy2010hera,

   title={Hera-JVM: a runtime system for heterogeneous multi-core architectures},

   author={McIlroy, R. and Sventek, J.},

   booktitle={Proceedings of the ACM international conference on Object oriented programming systems languages and applications},

   pages={205–222},

   year={2010},

   organization={ACM}

}

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Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores support different instruction set architectures, and the processor as a whole does not provide coherence between the different cores’ local memories. We present Hera-JVM, an implementation of the Java Virtual Machine which operates over the Cell processor, thereby making this platforms more readily accessible to mainstream developers. Hera-JVM supports the full Java language; threads from an unmodified Java application can be simultaneously executed on both the main PowerPC-based core and on the additional SPE accelerator cores. Migration of threads between these cores is transparent from the point of view of the application, requiring no modification to Java source code or bytecode. Hera-JVM supports the existing Java Memory Model, even though the underlying hardware does not provide cache coherence between the different core types. We examine Hera-JVM’s performance under a series of real-world Java benchmarks from the SpecJVM, Java Grande and Dacapo benchmark suites. These benchmarks show a wide variation in relative performance on the different core types of the Cell processor, depending upon the nature of their workload. Execution of these benchmarks on Hera-JVM can achieve speedups of up to 2.25x by using one of the Cell processor’s SPE accelerator cores, compared to execution on the main PowerPC-based core. When all six SPE cores are exploited, parallel workloads can achieve speedups of up to 13x compared to execution on the single PowerPC core.
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