Thread Block Compaction for Efficient SIMT Control Flow

Wilson W. L. Fung, Tor M. Aamodt
University of British Columbia, Vancouver, BC, Canada
17th IEEE International Symposium on High-Performance Computer Architecture, HPCA-17, 2011


   title={Thread Block Compaction for Efficient SIMT Control Flow},

   author={Fung, Wilson W. L. and Aamodt, Tor M.},

   booktitle={17th IEEE International Symposium on High-Performance Computer Architecture, HPCA-17},



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Manycore accelerators such as graphics processor units (GPUs) organize processing units into single-instruction, multiple data "cores" to improve throughput per unit hardware cost. Programming models for these accelerators encourage applications to run kernels with large groups of parallel scalar threads. The hardware groups these threads into warps/wavefronts and executes them in lockstep-dubbed single-instruction, multiple-thread (SIMT) by NVIDIA. While current GPUs employ a per-warp (or per-wavefront) stack to manage divergent control flow, it incurs decreased efficiency for applications with nested, data-dependent control flow. In this paper, we propose and evaluate the benefits of extending the sharing of resources in a block of warps, already used for scratchpad memory, to exploit control flow locality among threads (where such sharing may at first seem detrimental). In our proposal, warps within a thread block share a common blockwide stack for divergence handling. At a divergent branch, threads are compacted into new warps in hardware. Our simulation results show that this compaction mechanism provides an average speedup of 22% over a baseline perwarp, stack-based reconvergence mechanism, and 17% versus dynamic warp formation on a set of CUDA applications that suffer significantly from control flow divergence.
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