Creating HW/SW co-designed MPSoPC’s from high level programming models
Computer Science and Computer Engineering Department, University of Arkansas
International Conference on High Performance Computing and Simulation (HPCS), 2011
@inproceedings{cartwright2011creating,
title={Creating HW/SW co-designed MPSoPC’s from high level programming models},
author={Cartwright, E. and Ma, S. and Andrews, D. and Huang, M.},
booktitle={High Performance Computing and Simulation (HPCS), 2011 International Conference on},
pages={554–560},
year={2011},
organization={IEEE}
}
FPGA densities have continued to follow Moore’s law and can now support a complete multiprocessor system on programmable chip. The benefits of the FPGA include the ability to build a customized MPSoC system consisting of heterogeneous processing resources, interconnects and memory hierarchies that best match the requirements of each application. In this paper we outline a new approach that allows users to drive the generation of a complete hardware/software co-designed multiprocessor system on programmable chip from an unaltered standard high level programming model. We use OpenCL as our specification framework and show how key API’s are extracted and used to automatically create a distributed shared memory multiprocessor system on chip architecture for Xilinx FPGA’s. We show how OpenCL API’s are easily translated to hthreads, a hardware-based microkernel operating system to provide pthreads compliant run time services within the MPSoPC architecture.
November 12, 2011 by hgpu
