Automatic efficient data layout for multithreaded stencil codes on CPUs and GPUs

Julien Jaeger, Denis Barthou
Parallelisme, Reseaux, Systemes d’information, Modelisation (PRISM), CNRS : UMR8144 – Universite de Versailles Saint-Quentin-en-Yvelines
High Performance Computing conference (2012), hal-00793201, (28 February 2013)


   title={Automatic efficient data layout for multithreaded stencil codes on CPUs and GPUs},

   author={Jaeger, Julien and Barthou, Denis and others},

   booktitle={IEEE Proceedings of High Performance Computing conference},




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Stencil based computation on structured grids is a kernel at the heart of a large number of scientific applications. The variety of stencil kernels used in practice make this computation pattern difficult to assemble into a high performance computing library. With the multiplication of cores on a single chip, answering architectural alignment requirements became an even more important key to high performance. In addition to vector accesses, data layout optimization must also consider concurrent parallel accesses. In this paper, we develop a strategy to automatically generate stencil codes for multicore vector architectures, searching for the best data layout possible to answer architectural alignment problems. We introduce a new method for aligning multidimensional data structures, called multipadding, that can be adapted to specificities of multicores and GPUs architectures. We present multiple methods with different level of complexity. We show on different stencil patterns that generated codes with multipadding display better performances than existing optimizations.
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