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An FPGA-based Torus Communication Network

Marcello Pivanti, Sebastiano Fabio Schifano, Hubert Simma

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Tags: FPGA, High Energy Physics - Lattice, Network communications, Networks, Physics

February 14, 2011 by hgpu

PacketShader: a GPU-accelerated software router

Sangjin Han, Keon Jang, KyoungSoo Park, Sue Moon

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Tags: Computer science, CUDA, Network communications, nVidia, nVidia GeForce GTX 480, Software router

November 6, 2010 by hgpu

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A Study of Floating-Point Precision Tuning in Deep Learning Operators Implementations

Atlas CLI: Machine Learning (ML) Lifecycle & Transparency Manager

Scalable GPU-Based Integrity Verification for Large Machine Learning Models

transformers_tvm: Implementation of Encoder Decoder transformer on TVM

Enhancing Transformer Performance and Portability through Auto-tuning Frameworks

INT v.s. FP: A framework to compare low-bit integer and float-point formats

INT v.s. FP: A Comprehensive Study of Fine-Grained Low-bit Quantization Formats

AutoDock-GPU: AutoDock for GPUs and other accelerators

Architecting Tensor Core-Based Reductions for Irregular Molecular Docking Kernels

NCCLX: collective communication framework

Collective Communication for 100k+ GPUs

Tutoring LLM into a Better CUDA Optimizer

Tutoring LLM into a Better CUDA Optimizer

Adaptivity in AdaptiveCpp: Optimizing Performance by Leveraging Runtime Information During JIT-Compilation

Adaptivity in AdaptiveCpp: Optimizing Performance by Leveraging Runtime Information During JIT-Compilation

Kernel Library for LLM Serving

Compiler and Runtime Systems for Generative AI Models

Neptune: Advanced ML Operator Fusion for Locality and Parallelism on GPUs

Neptune: Advanced ML Operator Fusion for Locality and Parallelism on GPUs

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