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An FPGA-based Torus Communication Network

Marcello Pivanti, Sebastiano Fabio Schifano, Hubert Simma

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Tags: FPGA, High Energy Physics - Lattice, Network communications, Networks, Physics

February 14, 2011 by hgpu

PacketShader: a GPU-accelerated software router

Sangjin Han, Keon Jang, KyoungSoo Park, Sue Moon

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Tags: Computer science, CUDA, Network communications, nVidia, nVidia GeForce GTX 480, Software router

November 6, 2010 by hgpu

torchPDLP: Primal-Dual Linear Programming in PyTorch. In collaboration with AMD and IPAM

Accelerating a Linear Programming Algorithm on AMD GPUs

Benchmarks for Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs

Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs

kvcached: Elastic KV cache for dynamic GPU sharing and efficient multi-LLM inference

Towards Efficient and Practical GPU Multitasking in the Era of LLM

Bandicoot: C++ library for GPU accelerated linear algebra

Bandicoot: A Templated C++ Library for GPU Linear Algebra

Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference

Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference

Fused Kernel Library (FKL)

The Fused Kernel Library: A C++ API to Develop Highly-Efficient GPU Libraries

GPUHammer: Rowhammer Attacks on GPU Memories are Practical

GPUHammer: Rowhammer Attacks on GPU Memories are Practical

Block: Balance Loader of LLM Serving with Context, Knowledge and Predictive Scheduling

Block: Balancing Load in LLM Serving with Context, Knowledge and Predictive Scheduling

SIGMo: Scalable Isomorphism Graph Matching on GPUs

SIGMo: High-Throughput Batched Subgraph Isomorphism on GPUs for Molecular Matching

DGEMM without FP64 Arithmetic - using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme

DGEMM without FP64 Arithmetic – using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme

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