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A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Sparsh Mittal and Jeffrey S. Vetter

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Tags: 3D memory, bandwidth compression, cache, classification, cpu, GPU, HPC, main memory, NVM, Review

May 18, 2015 by sparsh0mittal

Intel® SHMEM: Device initiated shared memory based communication library

Intel(R) SHMEM: GPU-initiated OpenSHMEM using SYCL

AFOCL

Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL

miniLB: Lattice Botlzmann miniapp w/SYCL

miniLB: A Performance Portability Study of Lattice-Boltzmann Simulations

2domination

HPC acceleration of large (min, +) matrix products to compute domination-type parameters in graphs

MFC: Exascale simulation of multiphase/physics fluid dynamics

OpenACC offloading of the MFC compressible multiphase flow solver on AMD and NVIDIA GPUs

UVaFTLE: Lagrangian finite time Lyapunov exponent extraction for fluid dynamic applications

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL

HPCToolkit

Refining HPCToolkit for application performance analysis at exascale

Open Catalog of Best Practices for Modernization and Optimization

Optimizing the Weather Research and Forecasting Model with OpenMP Offload and Codee

Owl: Differential-based Side-Channel Leakage Detection for CUDA Applications

Owl: Differential-based Side-Channel Leakage Detection for CUDA Applications

pSTL-Bench: Micro-benchmark suite designed to evaluate the scalability and efficiency of parallel C++ STL implementations

Exploring Scalability in C++ Parallel STL Implementations

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