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An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness

Sunpyo Hong, Hyesoon Kim
Electrical and Computer Engineering, Georgia Institute of Technology
In ISCA ’09: Proceedings of the 36th annual international symposium on Computer architecture (2009), pp. 152-163.

@article{hong2009analytical,

   title={An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness},

   author={Hong, S. and Kim, H.},

   journal={ACM SIGARCH Computer Architecture News},

   volume={37},

   number={3},

   pages={152–163},

   year={2009},

   publisher={ACM}

}

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GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance bottlenecks of those parallel programs on GPU architectures to improve application performance is even more difficult. Current approaches rely on programmers to tune their applications by exploiting the design space exhaustively without fully understanding the performance characteristics of their applications.
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