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Porting to the Intel Xeon Phi: Opportunities and Challenges

C. Rosales
Texas Advanced Computing Center, The University of Texas at Austin, J.J. Pickle Research Campus, Building 196, Austin, Texas
Extreme Scaling Workshop (XSCALE13), 2013
@article{rosales2013porting,

   title={Porting to the Intel Xeon Phi: Opportunities and Challenges},

   author={Rosales, C},

   year={2013}

}

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This work describes the challenges presented by porting code to the Intel Xeon Phi coprocessor, as well as opportunities for optimization and tuning. We use micro-benchmarks, code segments, assembly listings and application level results to illustrate the key issues in porting to the Xeon Phi coprocessor, always keeping in mind both portability and performance. While executing code on the Xeon Phi in native mode is fairly straightforward it can be a challenge to achieve good performance. The complexity of optimization increases as one introduces offload, distributed offload, or symmetric execution modes. We will initially focus on the fundamental issues that can prevent acceptable performance in native execution, and then address the key issues in data transfers due to either offloaded regions or MPI exchanges with the host CPU. Some of the issues are of a generic nature and affect any code using heterogeneous execution – PCIe bandwidth bottleneck -, and others are specific to the Xeon Phi and its software environment – Host/MIC MPI exchanges. We will also make an effort to indicate which issues are specific to this platform and which are of general applicability. In particular we will draw comparisons between the data management models in the Intel Xeon Phi and in the NVIDIA CUDA environment.
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