15074

High Performance Histograms on SIMT and SIMD Architectures

M.E.R. Berger
Parallel and Distributed Systems group, Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology
Delft University of Technology, 2015

@phdthesis{berger2015high,

   title={High Performance Histograms on SIMT and SIMD Architectures},

   author={Berger, M.E.R.},

   year={2015}

}

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Using the histogram procedure, this work studies performance determining factors in computing in parallel on SIMD and SIMT devices. Modern graphics pro-cessing units (GPUs) support SIMT, multiple threads running the same instruction, whereas central processing units (CPUs) use SIMD, in which one instruction op-erates on multiple operands. As part of this work, a cross-technology framework is developed that allows testing a single-source histogram implementation on multiple devices, providing insight into the performance of various API – hardwareconfigurations. It is shown that in the presence of high contention, the implementation of atomic operations becomes of great influence on performance. This work provides guidelines for the choice between devices based on image features and hardware specifications.
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