A Survey of Techniques for Architecting Processor Components using Domain Wall Memory
Oak Ridge National Laboratory (ORNL)
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2016
Recent trends of increasing core-count and bandwidth/memory-wall have motivated the researchers to explore novel memory technologies for designing processor components such as cache, register file, shared memory, etc. Domain wall memory (DWM), also known as racetrack memory, is a promising emerging technology due to its non-volatility and very high density. However, use of DWM presents challenges due to characteristics of both DWM itself (e.g., requirement of shift operations, variable latency) and processor components. Recently, several techniques have been proposed to address these challenges. This paper presents a survey of architectural techniques for using DWM for designing components in both CPU and GPU. We discuss techniques related to performance, energy and reliability and also discuss works which compare DWM with other memory technologies. We also highlight the opportunities and obstacles in using DWM for designing processor components. This survey is expected to spark further research in this area and be useful for researchers, chip designers and computer architects.
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