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Automatic tuning matrix multiplication performance on graphics hardware

Changhao Jiang, M. Snir
Department of Computer Science, University of Illinois Urbana Champaign, 201 N. Goodwin Avenue, Urbana, IL 61801-2302
Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on (2005), pp. 185-194

@conference{jiang2005automatic,

   title={Automatic tuning matrix multiplication performance on graphics hardware},

   author={Jiang, C. and Snir, M.},

   booktitle={Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on},

   pages={185–194},

   isbn={076952429X},

   issn={1089-795X},

   year={2005},

   organization={IEEE}

}

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In order to utilize the tremendous computing power of graphics hardware and to automatically adapt to the fast and frequent changes in its architecture and performance characteristics, this paper implements an automatic tuning system to generate high-performance matrix-multiplication implementation on graphics hardware. The automatic tuning system uses a parameterized code generator to generate multiple versions of matrix multiplication, whose performances are empirically evaluated by actual execution on the target platform. An ad-hoc search engine is employed to search over the implementation space for the version that yields the best performance. In contrast to similar systems on CPUs, which utilize cache blocking, register tiling, instruction scheduling tuning strategies, this paper identifies and exploits several tuning strategies that are unique for graphics hardware. These tuning strategies include optimizing for multiple-render-targets, SIMD instructions with data packing, overcoming limitations on instruction count and dynamic branch instruction. The generated implementations have comparable performance with expert manually tuned version in spite of the significant overhead incurred due to the use of the high-level BrookGPU language.
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