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GPU-based parallelization for fast circuit optimization

Yifang Liu, Jiang Hu
Department of ECE, Texas A&M University, College Station, TX
Proceedings of the 46th Annual Design Automation Conference, DAC ’09

@conference{liu2009gpu,

   title={GPU-based parallelization for fast circuit optimization},

   author={Liu, Y. and Hu, J.},

   booktitle={Proceedings of the 46th Annual Design Automation Conference},

   pages={943–946},

   year={2009},

   organization={ACM}

}

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The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques and apply them on simultaneous gate sizing and threshold voltage assignment, which is often employed in practice for performance and power optimization. These techniques are aimed to fully utilize the benefits of GPU through efficient task scheduling and memory organization. Compared to conventional sequential computation, our techniques can provide up to 56x speedup without any sacrifice on solution quality.
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