Bridging the GPGPU-FPGA efficiency gap

Christopher W. Fletcher, Ilia A. Lebedev, Narges B. Asadi, Daniel R. Burke, John Wawrzynek
Massachusetts Institute of Technology, Cambridge, MA, and University of California at Berkeley, Berkeley, CA, USA
In Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays (2011), pp. 119-122.


   title={Bridging the GPGPU-FPGA efficiency gap},

   author={Fletcher, C.W. and Lebedev, I.A. and Asadi, N.B. and Burke, D.R. and Wawrzynek, J.},

   booktitle={Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays},





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This paper compares an implementation of a Bayesian inference algorithm across several FPGAs and GPGPUs, while embracing both the execution model and high-level architecture of a GPGPU. Our study is motivated by recent work in template-based programming and architectural models for FPGA computing. The comparison we present is meant to demonstrate the FPGA’s potential, while constraining the design to follow the microarchitectural template of more programmable devices such as GPGPUs. The FPGA implementation proves capable of matching the performance of a high-end Nvidia Fermi-based GPU – the most advanced GPGPU available to us at the time of this study. Further investigation shows that each FPGA core outperforms workstation GPGPU cores by a factor of ~ 3.14x, and mobile GPGPU cores by ~ 4.25x despite a ~ 4x reduction in core clock frequency. Using these observations, we discuss the efficiency gap between these two platforms, and the challenges associated with template-based programming models.
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