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Performance evaluation and optimization of random memory access on multicores with high productivity

Vaibhav Saxena, Yogish Sabharwal, Pramod Bhatotia
IBM Research – India, New Delhi, India
International Conference on High Performance Computing (HiPC), 2010

@inproceedings{saxena2010performance,

   title={Performance evaluation and optimization of random memory access on multicores with high productivity},

   author={Saxena, V. and Sabharwal, Y. and Bhatotia, P.},

   booktitle={High Performance Computing (HiPC), 2010 International Conference on},

   pages={1–10},

   year={2010},

   organization={IEEE}

}

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The slow progress in memory access latencies in comparison to CPU speeds has resulted in memory accesses dominating code performance. While architectural enhancements have benefited applications with data locality and sequential access, random memory access still remains a cause for concern. Several benchmarks have been proposed to evaluate the random memory access performance on multicore architectures. However, the performance evaluation models used by the existing benchmarks do not fully capture the varying types of random access behaviour arising in practical applications. In this paper, we propose a new model for evaluating the performance of random memory access that better captures the random access behaviour demonstrated by applications in practice. We use our model to evaluate the performance of two popular multicore architectures, the Cell and the GPU. We also suggest novel optimizations on these architectures that significantly boost the performance for random accesses in comparison to conventional architectures. Performance improvements on these architectures typically come at the cost of reduced productivity considering the extra programming effort involved. To address this problem, we propose libraries that incorporate these optimizations and provide innovatively designed programming interfaces that can be used by the applications to achieve good performance without loss of productivity.
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