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Understanding the impact of CUDA tuning techniques for Fermi

Yuri Torres, Arturo Gonzalez-Escribano, Diego R. Llanos
Departamento de Informatica, Universidad de Valladolid, Spain
International Conference on High Performance Computing and Simulation (HPCS), 2011

@inproceedings{torres2011understanding,

   title={Understanding the impact of CUDA tuning techniques for Fermi},

   author={Torres, Y. and Gonzalez-Escribano, A. and Llanos, D.R.},

   booktitle={High Performance Computing and Simulation (HPCS), 2011 International Conference on},

   pages={631–639},

   year={2011},

   organization={IEEE}

}

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While the correctness of an NVIDIA CUDA program is easy to achieve, exploiting the GPU capabilities to obtain the best performance possible is a task for CUDA experienced programmers. Typical code tuning strategies, like choosing an appropriate size and shape for the threadblocks, programming a good coalescing, or maximize occupancy, are inter-dependent. Moreover, the choices are also dependent on the underlying architecture details, and the global-memory access pattern of the designed solution. For example, the size and shapes of threadblocks are usually chosen to facilitate encoding (e.g. square shapes), while maximizing the multiprocessors’ occupancy. However, this simple choice does not usually provide the best performance results. In this paper we discuss important relations between the size and shapes of threadblocks, occupancy, global memory access patterns, and other Fermi architecture features, such as the configuration of the new transparent cache. We present an insight based approach to tuning techniques, providing lines to understand the complex relations, and to easily avoid bad tuning settings.
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