Optimisation and Parallelism in Synchronous Digital Circuit Simulators

John T. O’Donnell, Cordelia V. Hall
School of Computing Science, University of Glasgow, Glasgow, UK, G12 8QQ
IEEE International Conference on Computational Science and Engineering, 2012


   title={Optimisation and Parallelism in Synchronous Digital Circuit Simulators},

   author={ODonnell, John T and Hall, Cordelia V},

   booktitle={Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on},





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Digital circuit simulation often requires a large amount of computation, resulting in long run times. We consider several techniques for optimising a brute force synchronous circuit simulator: an algorithm using an event queue that avoids recalculating quiescent parts of the circuit, a marking algorithm that is similar to the event queue but that avoids a central data structure, and a lazy algorithm that avoids calculating signals whose values are not needed. Two target architectures for the simulator are used: a sequential CPU, and a parallel GPGPU. The interactions between the different optimisations are discussed, and the performance is measured while the algorithms are simulating a simple but realistic scalable circuit.
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