HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU
Dept. of Electrical and Computer Engineering, Rice University, Houston, TX
47th IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), 2013
@article{wu2013hspa,
title={HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU},
author={Wu, Michael and Wang, Guohui and Yin, Bei and Studer, Christoph and Cavallaro, Joseph R},
year={2013}
}
This paper compares two implementations of reconfigurable and high-throughput turbo decoders. The first implementation is optimized for an NVIDIA Kepler graphics processing unit (GPU), whereas the second implementation is for an Intel Ivy Bridge processor. Both implementations support max-log-MAP and log-MAP turbo decoding algorithms, various code rates, different interleaver types, and all block-lengths, as specified by HSPA+ and LTE-Advanced. In order to ensure a fair comparison between both implementations, we perform device-specific optimizations to improve the decoding throughput and error-rate performance. Our results show that the Intel Ivy Bridge processor implementation achieves up to 2x higher decoding throughput than our GPU implementation. In addition our CPU implementation requires roughly 4x fewer codewords to be processed in parallel to achieve its peak throughput.
December 4, 2013 by hgpu
