SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications

Thomas C.P. Chau, Maciej Kurek, James S. Targett, Jake Humphrey, George Skouroupathis, Alison Eele, Jan Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Leong, Peter Y.K. Cheung, Wayne Luk
Department of Computing, Imperial College London, UK
International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 141-148, 2014


   title={SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications},

   author={Chau, Thomas C.P. and Kurek, Maciej and Targett, James S. and Humphrey, Jake and Skouroupathis, George and Eele, Alison and Maciejowski, Jan and Cope, Benjamin and Cobden, Kathryn and Leong, Philip and Cheung, Peter Y.K. and Luk, Wayne},



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The Sequential Monte Carlo (SMC) method is a simulation-based approach to compute posterior distributions. SMC methods often work well on applications considered intractable by other methods due to high dimensionality, but they are computationally demanding. While SMC has been implemented efficiently on FPGAs, design productivity remains a challenge. This paper introduces a design flow for generating efficient implementation of reconfigurable SMC designs. Through templating the SMC structure, the design flow enables efficient mapping of SMC applications to multiple FPGAs. The proposed design flow consists of a parametrisable SMC computation engine, and an open-source software template which enables efficient mapping of a variety of SMC designs to reconfigurable hardware. Design parameters that are critical to the performance and to the solution quality are tuned using a machine learning algorithm based on surrogate modelling. Experimental results for three case studies show that design performance is substantially improved after parameter optimisation. The proposed design flow demonstrates its capability of producing reconfigurable implementations for a range of SMC applications that have significant improvement in speed and in energy efficiency over optimised CPU and GPU implementations.
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