Thorough Evaluation of GPU Shared Memory Load and Store Instructions
Department of Information Engineering, Hiroshima University, Kagamiyama 1-4-1, Higashi-Hiroshima, 739-8527 Japan
International Symposium on Computing and Networking, pp. 614-616, 2014
@article{okamoto2014thorough,
title={Thorough Evaluation of GPU Shared Memory Load and Store Instructions},
author={Okamoto, Satoshi and Ito, Yasuaki and Nakano, Koji and Bordim, Jacir L},
year={2014}
}
This work focuses on measuring the number of GPU clock cycles necessary to execute load/store instructions in both bank conflict and bank conflict-free shared memory access patterns. To this end, a varying number of parameters have been considered in the experiments, including the number of warps (w), the number of memory bank conflicts (k) as well as the number of load/store instructions (l) per warp. From the analysis of the experimental results, it was possible to obtain an estimate (E) on the number of the clock cycles necessary to execute l load/store instructions. The estimate is given by E = w * l * k * c1 + c2, where c1 and c2 are constants assuming values 1.047 and 337.7, respectively. From the above results, we believe that obtained estimated can be used as an approximation on the number of clock cycles necessary to execute load and store instructions.
January 13, 2015 by hgpu
