high performance computing on graphics processing units: hgpu.org

Yehia Arafa, Ammar ElWazir, Abdelrahman ElKanishy, Youssef Aly, Ayatelrahman Elsayed, Abdel-Hameed Badawy, Gopinath Chennupati, Stephan Eidenbenz, Nandakishore Santhi

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Tags: Computer science, CUDA, Energy-efficient computing, Measurement techniques, nVidia, nVidia GeForce GTX 1080 Ti, nVidia GeForce GTX Titan V, nVidia GeForce GTX Titan X, nVidia Titan RTX, PTX

February 23, 2020 by hgpu

Instructions’ Latencies Characterization for NVIDIA GPGPUs

Yehia Arafa, Abdel-Hameed Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan Eidenbenz

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Tags: Benchmarking, Computer science, CUDA, nVidia, nVidia GeForce GTX Titan X, nVidia Titan RTX, Performance, PTX, Tesla K40, Tesla P100, Tesla V100

May 23, 2019 by hgpu

CUDA au Coq: A Framework for Machine-validating GPU Assembly Programs

Benjamin Ferrell, Jun Duan, Kevin W. Hamlen

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Tags: Algorithms, Compilers, Computer science, CUDA, nVidia, PTX

May 15, 2019 by hgpu

Dissecting the NVidia Turing T4 GPU via Microbenchmarking

Zhe Jia, Marco Maggioni, Jeffrey Smith, Daniele Paolo Scarpazza

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Tags: Benchmarking, Computer science, CUDA, Deep learning, nVidia, Performance, PTX, Tesla P100, Tesla V100

March 24, 2019 by hgpu

Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering

Ricardo Nobre, Luis Reis, Joao M. P. Cardoso

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Tags: Computer science, nVidia, nVidia GeForce GTX 1070, OpenCL, Performance, PTX

October 28, 2018 by hgpu

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Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

MapReduce for Counting Word Frequencies with MPI and GPUs

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

SYCLCOMP Utilities

On the Compilation Performance of Current SYCL Implementations

M1 GPUs for (scientific) computations in C++

Seamless GPU acceleration for C++ based physics with the Metal Shading Language on Apple’s M series unified chips

CUB: Cooperative primitives for CUDA C++

Onesweep: A Faster Least Significant Digit Radix Sort for GPUs

Simulator and workload generator for Edge-to-Cloud environments

FELARE: Fair Scheduling of Machine Learning Applications on Heterogeneous Edge Systems

See all packages

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high performance computing on graphics processing units: hgpu.org

Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numerical Behaviors

Research and Development of Porting SYCL on QNX Operating System for High Parallelism

Improving Performance and Energy Efficiency of GPUs through Locality Analysis

LocalityGuru: A PTX Analyzer for Extracting Thread Block-level Locality in GPGPUs

SYCL-Bench: A Versatile Cross-Platform Benchmark Suite for Heterogeneous Computing

Automatic Kernel Generation for Volta Tensor Cores

GEVO: GPU Code Optimization using Evolutionary Computation

Verified Instruction-Level Energy Consumption Measurement for NVIDIA GPUs

Instructions’ Latencies Characterization for NVIDIA GPGPUs

CUDA au Coq: A Framework for Machine-validating GPU Assembly Programs

Dissecting the NVidia Turing T4 GPU via Microbenchmarking

Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering

Recent source codes

Rodinia Benchmarks for DPC++

DCA++: a state of the art implementation of the dynamical cluster approximation

tntorch - Tensor Network Learning with PyTorch

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

MapReduce for Counting Word Frequencies with MPI and GPUs

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

SYCLCOMP Utilities

M1 GPUs for (scientific) computations in C++

CUB: Cooperative primitives for CUDA C++

Simulator and workload generator for Edge-to-Cloud environments

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