Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU
School of Electrical Engineering, Seoul National University, Seoul, South Korea
Journal of Signal Processing Systems (3 November 2010), pp. 1-11
@article{jimemory,
title={Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU},
author={Ji, H. and Cho, J. and Sung, W.},
journal={Journal of Signal Processing Systems},
pages={1–11},
issn={1939-8018},
publisher={Springer}
}
Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.
November 22, 2010 by hgpu
