Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation

Kevin Andryc, Tedy Thomas, Russell Tessier
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003
arXiv:1606.06454 [cs.AR], (21 Jun 2016)


   title={Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation},

   author={Andryc, Kevin and Thomas, Tedy and Tessier, Russell},






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We present a customizable soft architecture which allows for the execution of GPGPU code on an FPGA without the need to recompile the design. Issues related to scaling the overlay architecture to multiple GPGPU multiprocessors are considered along with application-class architectural optimizations. The overlay architecture is optimized for FPGA implementation to support efficient use of embedded block memories and DSP blocks. This architecture supports direct CUDA compilation of integer computations to a binary which is executable on the FPGA-based GPGPU. The benefits of our architecture are evaluated for a collection of five standard CUDA benchmarks which are compiled using standard GPGPU compilation tools. Speedups of 44x, on average, versus a MicroBlaze microprocessor are achieved. We show dynamic energy savings versus a soft-core processor of 80% on average. Application-customized versions of the soft GPGPU can be used to further reduce dynamic energy consumption by an average of 14%.
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