An Implementation of Real-Time Phased Array Radar Fundamental Functions on a DSP-Focused, High-Performance, Embedded Computing Platform
School of Electrical and Computer Engineering, University of Oklahoma, 3190 Monitor Avenue, Norman, OK 73019, USA
Aerospace, 3(3), 28, 2016
@inproceedings{yu2016implementation,
title={An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform},
author={Yu, Xining and Zhang, Yan and Patel, Ankit and Zahari, Allen and Weber, Mark},
booktitle={SPIE Defense+ Security},
pages={982913–982913},
year={2016},
organization={International Society for Optics and Photonics}
}
This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of general purpose digital signal processors. First, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on a Micro Telecom Computing Architecture (MTCA) chassis using the Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebones design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including the Open Computing Language.
September 10, 2016 by hgpu
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