Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File
IIT, Hyderabad, India
IEEE International Conference on VLSI Design (VLSID)
@inproceedings{ref83,
title={Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File},
year={"2017"},
author={"SparshMittalandHaonanWangandAdwaitJogandJeffreyVetter"},
booktitle={"IEEEInternationalConferenceonVLSIDesign(VLSID)"},
address={"Hyderabad},
keywords={"GPU}
}
Modern graphics processing units (GPUs) are using increasingly larger register file (RF) which occupies a large fraction of GPU core area and is very frequently accessed. This makes RF vulnerable to soft-errors (SE). In this paper, we present two techniques for improving SE resilience of GPU RF. First, we propose compressing the RF values for reducing the number of vulnerable bits. We leverage value similarity and the presence of narrow-width values to perform compression at warp or thread-level, respectively. Second, we propose selective hardening to design a portion of register entry with SE immune circuits. By collectively using these techniques, higher resilience can be provided with lower overhead. Without hardening, our warp and thread-level compression techniques bring 47.0\% and 40.8\% reduction in SE vulnerability, respectively.
November 1, 2016 by sparsh0mittal
