Scalable communication for high-order stencil computations using CUDA-aware MPI
Department of Computer Science, Aalto University, Konemiehentie 2, 02150 Espoo, Finland
arXiv:2103.01597 [cs.DC], (2 Mar 2021)
@misc{pekkilä2021scalable,
title={Scalable communication for high-order stencil computations using CUDA-aware MPI},
author={Johannes Pekkilä and Miikka S. Väisälä and Maarit J. Käpylä and Matthias Rheinhardt and Oskar Lappi},
year={2021},
eprint={2103.01597},
archivePrefix={arXiv},
primaryClass={cs.DC}
}
Modern compute nodes in high-performance computing provide a tremendous level of parallelism and processing power. However, as arithmetic performance has been observed to increase at a faster rate relative to memory and network bandwidths, optimizing data movement has become critical for achieving strong scaling in many communication-heavy applications. This performance gap has been further accentuated with the introduction of graphics processing units, which can provide by multiple factors higher throughput in data-parallel tasks than central processing units. In this work, we explore the computational aspects of iterative stencil loops and implement a generic communication scheme using CUDA-aware MPI, which we use to accelerate magnetohydrodynamics simulations based on high-order finite differences and third-order Runge-Kutta integration. We put particular focus on improving intra-node locality of workloads. In comparison to a theoretical performance model, our implementation exhibits strong scaling from one to 64 devices at 50%–87% efficiency in sixth-order stencil computations when the problem domain consists of 256^3–1024^3 cells.
March 7, 2021 by hgpu