26723

FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL

K. Kamalakkannan, G.R. Mudalige, I.Z. Reguly, S.A. Fahmy
University of Warwick, UK
10th International Workshop on OpenCL and SYCL (IWOCL & SYCLcon 2022), 2022

@inproceedings{kamalakkannan2022fpga,

   title={FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL},

   author={Kamalakkannan, Kamalavasan and Mudalige, Gihan and Reguly, Istvan and Fahmy, Suhaib},

   booktitle={International Workshop on OpenCL},

   pages={1–11},

   year={2022}

}

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We explore the design and development of structured-mesh based solvers on current Intel FPGA hardware using the SYCL programming model. Two classes of applications are targeted : (1) stencil applications based on explicit numerical methods and (2) multidimensional tridiagonal solvers based on implicit methods. Both classes of solvers appear as core modules in a wide-range of realworld applications ranging from CFD to financial computing. A general, unified workflow is formulated for synthesizing them on Intel FPGAs together with predictive analytic models to explore the design space to obtain near-optimal performance. Performance of synthesized designs, using the above techniques, for two non-trivial applications on an Intel PAC D5005 FPGA card is benchmarked. Results are compared to performance of optimized parallel implementations of the same applications on a Nvidia V100 GPU. Observed runtime results indicate the FPGA providing better or matching performance to the V100 GPU. However, more importantly the FPGA solutions provide 59%-76% less energy consumption for their largest configurations, making them highly attractive for solving workloads based on these applications in production settings. The performance model predicts the runtime of designs with high accuracy with less than 5% error for all cases tested, demonstrating their significant utility for design space explorations. With these tools and techniques, we discuss determinants for a given structuredmesh code to be amenable to FPGA implementation, providing insights into the feasibility and profitability of a design, how they can be codified using SYCL and the resulting performance.
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