29006

Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System

Tsung-Wei Huang, Boyang Zhang, Dian-Lun Lin, Cheng-Hsiang Chiu
The University of Wisconsin at Madison, Madison, Wisconsin, USA
ACM International Symposium on Physical Design (ISPD), Taipei, Taiwan, 2024

@article{huang2024parallel,

   title={Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System},

   author={Huang, Tsung-Wei and Zhang, Boyang and Lin, Dian-Lun and Chiu, Cheng-Hsiang},

   year={2024}

}

Static timing analysis (STA) is an integral part in the overall design flow because it verifies the expected timing behaviors of a circuit. However, as the circuit complexity continues to enlarge, there is an increasing need for enhancing the performance of existing STA algorithms using emerging heterogeneous parallelism that comprises manycore central processing units (CPUs) and graphics processing units (GPUs). In this paper, we introduce several state-of-the-art STA techniques, including task-based parallelism, task graph partition, and GPU kernel algorithms, all of which have brought significant performance benefits to STA applications. Motivated by these successful results, we will introduce a task-parallel programming system to generalize our solutions to benefit broader scientific computing applications.
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