Towards a Software Transactional Memory for Graphics Processors
Department of Computer Science and Engineering, Chalmers University of Technology, Goteborg, Sweden
Eurographics Symposium on Parallel Graphics and Visualization (2010)
@article{cederman2010towards,
title={Towards a Software Transactional Memory for Graphics Processors},
author={Cederman, D. and Tsigas, P. and Chaudhry, M.T.},
year={2010}
}
The introduction of general purpose computing on many-core graphics processor systems, and the general shift in the industry towards parallelism, has created a demand for ease of parallelization. Software transactional memory (STM) simplifies development of concurrent code by allowing the programmer to mark sections of code to be executed concurrently and atomically in an optimistic manner. In contrast to locks, STMs are easy to compose and do not suffer from deadlocks. We have designed and implemented two STMs for graphics processors, one blocking and one non-blocking. The design issues involved in the designing of these two STMs are described and explained in the paper together with experimental results comparing the performance of the two STMs.
March 4, 2011 by hgpu
