Parallel cross-layer optimization of high-level synthesis and physical design

James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng
ECEE, University of Colorado, Boulder, CO, USA
16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011


   title={Parallel cross-layer optimization of high-level synthesis and physical design},

   author={Williamson, J. and Lu, Y. and Shang, L. and Zhou, H. and Zeng, X.},

   booktitle={Proceedings of the 16th Asia and South Pacific Design Automation Conference},



   organization={IEEE Press}


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Integrated circuit (IC) design automation has traditionally followed a hierarchical approach. Modern IC design flow is divided into sequentially-addressed design and optimization layers; each successively finer in design detail and data granularity while increasing in computational complexity. Eventual agreement across the design layers signals design closure. Obtaining design closure is a continual problem, as lack of awareness and interaction between layers often results in multiple design flow iterations. In this work, we propose parallel cross-layer optimization, in which the boundaries between design layers are broken, allowing for a more informed and efficient exploration of the design space. We leverage the heterogeneous parallel computational power in current and upcoming multi-core/many-core computation platforms to suite the heterogeneous characteristics of multiple design layers. Specifically, we unify the highlevel and physical synthesis design layers for parallel cross-layer IC design optimization. In addition, we introduce a massively-parallel GPU floorplanner with local and global convergence test as the proposed physical synthesis design layer. Our results show average performance gains of 11X speed-up over state-of-the-art.
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