GCS: High-Performance Gate-Level Simulation with GP-GPUs

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
Department of Computer Science and Engineering, University of Michigan
Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09


   title={GCS: High-performance gate-level simulation with GP-GPUs},

   author={Chatterjee, D. and DeOrio, A. and Bertacco, V.},

   booktitle={Proceedings of the Conference on Design, Automation and Test in Europe},




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In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design.
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