Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips
DFT Engineering, NVIDIA Corp., 2701 San Tomas Expy, Santa Clara, CA 95050, USA
IEEE 29th VLSI Test Symposium (VTS), 2011
@inproceedings{sanghani2011design,
title={Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips},
author={Sanghani, A. and Yang, B. and Natarajan, K. and Liu, C.},
booktitle={VLSI Test Symposium (VTS), 2011 IEEE 29th},
pages={219–224},
organization={IEEE},
year={2011}
}
We present the design and implementation details of a time-division demultiplexing/multiplexing based scan architecture using serializer/deserializer. This is one of the key DFT features implemented on NVIDIA’s Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer/deserializer module design, test timing consideration, design rule and test pattern verification. Finally, we show silicon data collected from Fermi GPUs.
June 24, 2011 by hgpu
