Design and performance evaluation of a digital wideband receiver on a hybrid computing platform
Computer Engineering Program, California State University, Fullerton, CA 92831, USA
IEEE Instrumentation and Measurement Technology Conference (I2MTC), 2011
@inproceedings{george2011design,
title={Design and performance evaluation of a digital wideband receiver on a hybrid computing platform},
author={George, K. and Chen, C.I.H.},
booktitle={Instrumentation and Measurement Technology Conference (I2MTC), 2011 IEEE},
pages={1–5},
organization={IEEE},
year={2011}
}
Design and implementation of a modern radar receiver that is capable of rapidly searching a large frequency range with maximum sensitivity in real time presents a challenge. Such a receiver not only has stringent operational requirements like high instantaneous dynamic range (IDR), multiple signal detection capability, wider bandwidth and also high frequency resolution. Currently, operating speeds of digital processors are not on par with state-of-the-art ADCs. To overcome this impediment, researchers are exploring methods of offloading the computational intensive tasks to specialized hardware accelerators. A 3 giga-sample-per-second (GSPS) wideband digital receiver system implemented on a unique hybrid computing platform, which is composed of two Tesla C2050 GPUs and a Xilinx Virtex-5 FPGA, is presented. Drastically improving its performance over its predecessors, the proposed receiver system detects five simultaneous signals in 1.25 GHz bandwidth (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture performs a high-resolution spectral estimation and employs a hardware efficient platform for detecting multiple signals before the next set of buffered data arrives for processing.
July 12, 2011 by hgpu
