A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

Alexandre S. Nery, Nadia Nedjah, Felipe M.G. Franca, Lech Jozwiak
LAM – Computer Architecture and Microelectronics Laboratory, Systems Engineering and Computer Science Program, COPPE, Universidade Federal do Rio de Janeiro, Brazil
14th Euromicro Conference on Digital System Design (DSD), 2011


   title={A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations},

   author={Nery, A.S. and Nedjah, N. and Franca, F.M.G. and Jozwiak, L.},

   booktitle={Digital System Design (DSD), 2011 14th Euromicro Conference on},





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The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.
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