high performance computing on graphics processing units: hgpu.org

This work envisions that in the near future, GPUlike architectures will find their way to embedded systems. Accompanied by a small RISC control core, they will not merely be a hardware accelerator, but the heart of the system itself. Taking a state-of-the-art GPU, a baseline architecture is constructed with the embedded context in mind. Next, by taking three sample applications-a FIR filter, a video decoder and a vision processing pipeline-it is shown that having no direct inter-cluster communication leads to inefficiencies. It is then argued that the most logical part of the design space to focus on, is message passing in a 1-dimensional ring topology. Within this sub-space, three different configurations-register file, FIFO queue, and segmented bus communication-are explored and compared in terms of chip area, cycle overhead, and communication flexibility. FIFO queue communication is concluded to be the most area efficient solution, the segmented bus however is best in terms of communication flexibility and cycle overhead.