An FPGA-based processing pipeline for high definition stereo video

Pierre Greisen, Simon Heinzle, Markus Gross, Andreas Peter Burg
ETH Zurich, 8092 Zurich, Switzerland
EURASIP Journal on Image and Video Processing (ISSN: 1687-5176), vol. 2011, 2011


   title={An FPGA-based processing pipeline for high definition stereo video},

   author={Greisen, P. and Heinzle, S. and Gross, M. and Burg, A.},

   journal={EURASIP Journal on Image and Video Processing},







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This paper presents a real-time processing platform for high definition stereo video. The system is capable to process stereo-video streams at resolutions up to 1920×1080 at 30 frames per second (1080p30). In the hybrid FPGA-GPU-CPU system, a high-density FPGA is used to perform not only the low-level image processing tasks such as color interpolation and cross-image color correction, but also to carry out radial undistortion, image rectification, and disparity estimation. We show how the corresponding algorithms can be implemented very efficiently in programmable hardware, relieving the GPU from the burden of these tasks. Our FPGA implementation results are compared to corresponding GPU implementations and to other implementations reported in the literature.
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