Model-Driven Tile Size Selection for DOACROSS Loops on GPUs
Programming Languages and Compilers Group, School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Proceedings of the 17th international conference on Parallel processing (Euro-Par’11), 2011
@inproceedings{Di:2011:MTS:2033408.2033456,
author={Di, Peng and Xue, Jingling},
title={Model-driven tile size selection for DOACROSS loops on GPUs},
booktitle={Proceedings of the 17th international conference on Parallel processing – Volume Part II},
series={Euro-Par’11},
year={2011},
isbn={978-3-642-23396-8},
location={Bordeaux, France},
pages={401–412},
numpages={12},
url={http://dl.acm.org/citation.cfm?id=2033408.2033456},
acmid={2033456},
publisher={Springer-Verlag},
address={Berlin, Heidelberg}
}
DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make tiling legal and exploit wavefront parallelism across the tiles and within a tile. Thus, tile size selection, which is performance-critical, becomes more complex for DOACROSS loops than DOALL loops on GPUs. This paper presents a model-driven approach to automating this process. Validation using 1D, 2D and 3D SOR solvers shows that our framework can find the tile sizes for these representative DOACROSS loops to achieve performances close to the best observed for a range of problem sizes tested.
February 20, 2012 by hgpu
