An innovative compilation tool-chain for embedded multi-core architectures

M. Torquati, M. Vanneschi, M. Amini, S. Guelton, R. Keryell, V. Lanore, F.-X. Pasquier, M. Barreteau, R. Barrere, T. Petrisor, E. Lenormand, C. Cantini, F. De Stefani
Computer Science Department, University of Pisa, Italy
Embedded World Conference, 2012


   title={An innovative compilation tool-chain for embedded multi-core architectures},

   author={Torquati, M. and Vanneschi, M. and Amini, M. and Guelton, S. and Keryell, R. and Lanore, V. and Pasquier, FX and Barreteau, M. and Barrere, R. and Petrisor, T. and others},



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In this paper, we propose a compilation tool-chain supporting the effective exploitation of multi-core architectures offering hundreds of cores. The tool-chain leverages on both the application requirements and the platform-specific features to provide developers with a powerful parallel-programming environment able to generate efficient parallel code. The design of parallel applications follows a semi-automatic approach enabling the programmer to transfer to back-end tools platform-specific code generation and optimization, thus making possible to avoid the clobbering of code with non-portable and complex directives. The programmer can graphically parallelize the application (mainly data-streaming ones) for the target platform using Thales’ Spear Design Environment. The resulting parallelization is generated under the form of an Intermediate Representation, which is then passed to the back-end tools (HPC Project’s Par4All) that generates efficient target code. We present the results obtained parallelizing a small subset of the RT-STAP radar algorithm and the Chirp filtering algorithm on standard multi-core and on nVidia GPUs.
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