Parallel Nonbinary LDPC Decoding on GPU
Department of Electrical and Computer Engineering, Rice University, Houston, Texas 77005
46th Asilomar Conference on Signals, Systems, and Computers (ASILOMAR 2012), 2012
@inproceedings{Guohui:Asilomar2012,
author={Guohui Wang and Hao Shen and Bei Yin and Michael Wu and Yang Sun and Joseph R. Cavallaro},
booktitle={the 46th Asilomar Conference on Signals, Systems and Computers},
title={Parallel Nonbinary {LDPC} Decoding on {GPU}},
year={2012},
month={Nov.}
}
Nonbinary Low-Density Parity-Check (LDPC) codes are a class of error-correcting codes constructed over the Galois field GF(q) for q > 2. As extensions of binary LDPC codes, nonbinary LDPC codes can provide better error-correcting performance when the code length is short or moderate, but at a cost of higher decoding complexity. This paper proposes a massively parallel implementation of a nonbinary LDPC decoding accelerator based on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The implementation maps the Min-Max decoding algorithm to GPU’s massively parallel architecture. We highlight the methodology to partition the decoding task to a heterogeneous platform consisting of the CPU and GPU. The experimental results show that our GPUbased implementation can achieve high throughput while still providing great flexibility and scalability.
November 29, 2012 by hgpu
