high performance computing on graphics processing units: hgpu.org

The development of a standardised testing methodology for side-channel resistance of cryptographic devices is an issue that has received recent focus from standardisation bodies such as NIST. Statistical techniques such as hypothesis and significance testing appear to be ideally suited for this purpose. In this work we evaluate the candidacy of three such tests: a emph{t}-test proposed by Cryptography Research Inc., and two mutual information-based tests. We compare the detection tests in a theoretical setting by conducting an emph{a priori} statistical power analysis, covering previously unforeseen problems arising from multiple hypothesis testing, and analyse the practical application of the tests through a case study using an implementation of the AES on an ARM7 microcontroller, demonstrating a trade-off between test genericity and data and computational complexity.