Dissecting the NVIDIA Blackwell Architecture with Microbenchmarks
Dept. of Computer Information Sciences, University of Delaware, Newark, US
arXiv:2507.10789 [cs.DC], (14 Jul 2025)
@misc{jarmusch2025dissectingnvidiablackwellarchitecture,
title={Dissecting the NVIDIA Blackwell Architecture with Microbenchmarks},
author={Aaron Jarmusch and Nathan Graddon and Sunita Chandrasekaran},
year={2025},
eprint={2507.10789},
archivePrefix={arXiv},
primaryClass={cs.DC},
url={https://arxiv.org/abs/2507.10789}
}
The rapid development in scientific research provides a need for more compute power, which is partly being solved by GPUs. This paper presents a microarchitectural analysis of the modern NVIDIA Blackwell architecture by studying GPU performance features with thought through microbenchmarks. We unveil key subsystems, including the memory hierarchy, SM execution pipelines, and the SM sub-core units, including the 5th generation tensor cores supporting FP4 and FP6 precisions. To understand the different key features of the NVIDIA GPU, we study latency, throughput, cache behavior, and scheduling details, revealing subtle tuning metrics in the design of Blackwell. To develop a comprehensive analysis, we compare the Blackwell architecture with the previous Hopper architecture by using the GeForce RTX 5080 and H100 PCIe, respectively. We evaluate and compare results, presenting both generational improvements and performance regressions. Additionally, we investigate the role of power efficiency and energy consumption under varied workloads. Our findings provide actionable insights for application developers, compiler writers, and performance engineers to optimize workloads on Blackwell-based platforms, and contribute new data to the growing research on GPU architectures.
July 20, 2025 by hgpu
Your response
You must be logged in to post a comment.
